a) Field of the Invention
The present invention relates to manufacture of semiconductor devices such as LSI, and more particularly to a method of manufacturing a semiconductor device capable of easily forming a fine connection hole having a high aspect ratio (a hole having a depth larger than a hole diameter).
b) Description of the Related Art
A method as illustrated in FIGS. 19 to 21 is known to form a connection hole during manufacture of LSI.
In the process illustrated in FIG. 19, a resist layer 3 is formed on an insulating film 2, such as silicon oxide, which covers the surface of a substrate 1. Holes 3a and 3b with a desired connection hole pattern are formed in the resist layer 3 by well-known exposure and development processes.
Next, in the process illustrated in FIG. 20, connection holes 2a and 2b corresponding to the holes 3a and 3b using the resist layer 3 as an etching mask. This selective etching process may be performed by a single process of anisotropic dry etching. However, if isotropic wet or dry etching is first performed and then anisotropic dry etching is performed, the connection hole 2a, 2b can be formed whose step at the opening thereof can be alleviated as shown in FIG. 20. The resist layer 3 is removed after etching.
Thereafter, in the process illustrated in FIG. 21, wiring material such as Al is deposited on the upper surface of the substrate. This deposited layer is patterned by well-known photolithography and selective etching to form wiring layers 4A and 4B filling the connection holes 2a and 2b.
The substrate 1 may be or may not be preliminarily provided with interconnections formed on the substrate surface via an insulating layer. If the substrate surface is formed with interconnections, the wiring layers 4A and 4B are usually connected to the interconnections on the substrate surface, whereas if the substrate surface is not formed with interconnections, the wiring layers 4A and 4B are usually connected to impurity doped regions in the substrate surface layer.
Since the step at the opening of the connection hole 2a, 2b is alleviated as shown in FIG. 20, the step coverage of the wiring layers 4A and 4B can be improved as shown in FIG. 21.
With the above-described conventional method, the insulating film is selectively dry etched by using the resist layer as the mask to form connection holes. Therefore, as the aspect ratio (ratio of hole depth to hole diameter) of a connection hole becomes large, it becomes difficult to supply etchant ions to the bottom of a connection hole with finely controlled directivity.
Further, if isotropic wet or dry etching is performed for alleviating the step at an opening of a connection hole, the number of manufacture steps increases.
Still further, if connection holes 2a and 2b are formed on impurity doped regions in the substrate surface layer, plasma etchant reaches via the connection holes the surfaces of impurity doped regions. Therefore, damage layers with crystal defects or the like may be formed, or excessive etching and deposition of by-product may occur. In this case, annealing for relieving damages or dry etching for removing the damage layer is performed, increasing the number of manufacture steps.